1. Field Of The Invention
The invention relates to a semiconductor memory having storage cells comprising MOS selector transistors operated by a drive line, and storage capacitors connected to the selector transistors, wherein the selector transistors are produced in accordance with the V-MOS technique.
2. Description Of The Prior Art
Single-transistor storage cells constructed in the MOS technique are known (see e.g. Electronics, Sept. 31, 1973, pages 116 to 121). These single-transistor storage cells comprise a selector transistor and a storage capacitor connected to the selector transistor. The selector transistor is connected by its control electrode to the word line of the semiconductor memory. The controlled path of the selector transistor is connected between a bit line and the storage capacitor. The other terminal of the storage capacitor is connected to a fixed voltage, e.g. the voltage VDD. The information to be stored in the storage cell is determined by the charge of the storage capacitor. The write-in and read-out of an item of information into and out of the storage cell is effected via the selector transistor, when the latter is operated from the word line.
Heretofore, the design of single-transistor storage cells constructed in the MOS technique has been such that the storage capacitor is arranged adjacent to the selector transistor on a semiconductor substrate. However, this has the disadvantage that a relatively large space requirement was needed to construct a storage cell.
It is also known that it is possible to construct MOS transistors in a semiconductor substrate employing the so-called V-MOS technique (see e.g. Solid State Electronics, 1976, vol. 19, pages 159 to 166, Electronics Letters, Sept. 20, 1973, vol. 19, No. 19, pages 457 to 458). In this V-MOS technique, on a silicon semiconductor substrate there is applied an epitaxial layer in which the transistor is arranged. Here the control electrode is formed in that a V-shaped groove is etched into the epitaxial layer, the groove is insulated, by an insulating layer of silicon oxide, whereupon the terminal for the control electrode of the transistor is applied. The controlled electrodes of the transistor can be arranged adjacent the control electrode in the epitaxial layer. The channel of the MOS transistor is formed along the edges of the V-shaped groove. Reference is made to the aforementioned publications in respect of the properties and advantages of the V-MOS technique and the production method.